1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a construction of a static random access memory (hereinafter SRAM) cell and the fabrication method thereof.
2. Discussion of the Related Art
FIGS. 1 and 2 are plan views showing a layout of an SRAM cell according to the conventional art. As shown in FIG. 1, the conventional SRAM cell includes a plurality of active regions 93,94,96 and a polysilicon line 95, a polysilicon interconnection line 12 and a word line 97 formed on the active region 93,94. A transistor TPA is formed between the active region 96 and the polysilicon line 95. A first node (N1) is formed between the active region 93 and the polysilicon line 95, and a second node (N2) connects the active region 96 and a line 12. A transistor TPB is formed at the crossed point of the line I2 and the active region 93. The first node (N1) is formed at the point where the end of the line 95 crosses a mid portion of the active region 93. A transistor (T1) is formed where the active region 93 crosses the word line 97. At the active region 93 formed between the transistor TPB and the transistor T1 is an interconnection line I1 formed of an active layer material. One end of the word line 97 and one end of the transistor (T2) are crossed in the active region 94. The transistors (TPA,TPB) are generally called drive transistors, and the transistors (T1,T2) are commonly called access transistors.
FIG. 2 is a plan view showing a layout of a split word line cell according to the conventional art. Referring to FIG. 2, the conventional SRAM cell having a split word line cell includes a plurality of active regions 90,91, polysilicon lines (N1,N2), and word lines (WL1,WL2) formed on the active regions 90,91. A transistor (T1) is formed where the line (N1) and the active region 90 cross each other, and a transistor (T3) is formed where the word line (WL1) and the active region 90 cross. A transistor (T4) is formed where the active region 91 and the word line (WL2) cross each other.
In the SRAM cell of FIG. 2, local interconnection lines (I 1,12) are defined by a buried N+ line. A common drain of the transistors (T1,T3) and a gate of the transistor (T2) are electrically connected by the local interconnection line (I1). A common drain of the transistors (T4,T2) and a gate of the transistor (T1) are electrically connected by the local interconnection line (I2).
In the SRAM cell of FIG. 1, the active diffusion region 93 and the polysilicon line (I2) are used for the connection of the two nodes (N1,N2). The active diffusion region 93 and the polysilicon line (I2) each have different resistance values. Since the polysilicon and the diffusion region have each different resistances, and different line lengths, the SRAM cell is in an asymmetrical condition, which means that the local interconnection lines (I1,I2) of the conventional SRAM of FIG. 1 are defined as different layers. That is, one is an N+ diffusion layer, and the other is a polysilicon deposition layer. The two are composed of different materials. Thus, the resistances of the nodes (N1,N2) are different, which causes the cell to be more unstable and different currents to flow in the transistors (T1,T2). Accordingly, the cell is asymmetrical when the transistors are turned on.
Moreover, the conventional SRAM cell of FIG. 1 has a small cell size, but the cells are formed asymmetrically having a 45.degree. layout. Therefore, resolution is not good in a super high resolution illumination control (SHRINK), a lithography, or a phase inversion mask. Also, a metal design rule becomes tight. In addition, a plurality of active regions 93,94,96 (FIG. 1) in the SRAM cell increases the cell size and requires a plurality of contact holes to be formed during the wiring of ground lines. As a result, the ground resistance value of each drive transistor is made different.
In the conventional split word line cell shown in FIG. 2, each interconnection line (I1,I2) is defined as a diffusion layer formed of an identical material and an identical layer to improve the asymmetry problem of the SRAM cell shown in FIG. 1. However, since the SRAM cell has a plurality of active regions 90,91, the cell size occupies a large area and a plurality of contact holes must be formed when wiring a ground line, resulting in a different ground resistance value for each drive transistor.